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| 78m6618 octal power and energy measurement ic data sheet ds_6618_005 march 2011 rev. 1.4 ? 2011 teridian semiconductor corporation 1 a ? maxim ? integrated ? products ? brand ? 19-5346; rev 3/11 description the teridian 78m6618 is a highly integrated ic for independent monitoring and measurement of up to eight single-phase ac outlets. with multiple host interface options, an integrated lcd driver, and conf igurable i/os, the device is ideal for metered power distribution units (pdus) and rack enclosures for the data center, as well as intelligent power strips and subpanels in the grid-friendly digital home. at the measurement interface, the device provides 10 analog inputs for interfacing to voltage and current sensors. scaled voltages from the sensors are fed to our single converter technology ? that uses a 21-bit delta-sigma adc, independent 32-bit compute engine (ce), digital temperature compensation, and precision voltage references to provide better than 0.5% accuracy over a wide 2000:1 dynamic range. the integrated mpu core and 128kb of flash memory provides a flexible means of configuration, postprocessing, data formatting, interfacing to host processor through a uart or spi? interface, displaying output data to an lcd, or using dio pins for intelligent relay control. complete firmware for common applications is available from teridian and can be loaded into the ic during manufacturing test. alternatively, a complete array of ice, development tools, and programming libraries are available to allow customization mpu code for each application. features ? < 0.5% wh accuracy over wide 2000:1 current range and over temperature ? exceeds iec 62053/ansi c12.20 standards ? voltage reference < 40ppm/c ? 10 sensor inputsv3p3 referenced ? 21-bit delta-sigma adc with independent 32-bit compute engine (ce) ? 8-bit mpu (80515), one clock cycle per instruction with 4kb mpu xram ? 128kb flash with security ? integrated ice for mpu debug ? 32khz time base with hardware watchdog timer ? uart and high-speed slave spi host interface options ? up to 19 general-purpose 5v tolerant i/o pins ? lcd driver (up to 70 pixels) ? packaged in a lead(pb)-free/rohs-compliant (6/6) 68-pin qfn ? robust sub-metering application firmware: o true rms calculations for current, voltage, line frequency, real power, reactive power, apparent power, and power factor o accumulated watt-hours, kilowatt-hours, and cost o intelligent switch control at zero crossings o digital temperature compensation o phase compensation ( 15 ) o quick calibration routines o 46-64hz line frequency range with same calibration o programmable alarm thresholds o high-level uart communication protocols o high-level spi communication protocols single converter technology is a registered trademark of maxim integrated products, inc. spi is a trademark of motorola, inc. downloaded from: http:///
78m6618 data sheet ds_6618_005 2 rev. 1. 4 table of contents 1 hardware functional description ................................................... ................................................... 5 1.1 hardware overview ................................................... ................................................... ............... 5 1.2 device reset ................................................... ................................................... .......................... 7 1.3 power management ................................................... ................................................... ............... 7 1.3.1 v oltage regulator ................................................... ................................................... ...... 7 1.3.2 power fault management ................................................... ............................................. 7 1.3.3 brownout ................................................... ................................................... .............. 7 1.3.4 sleep mode ................................................... ................................................... ............. 7 1.4 analog front end (afe) ................................................... ................................................... ......... 7 1.4.1 analog current and voltage inputs ................................................... .............................. 8 1.5 digital computation engine (ce) ................................................... ............................................. . 8 1.6 80515 mpu core ................................................... ................................................... ................... 8 1.6.1 sfr ................................................... ................................................... ............................ 9 1.7 xram ................................................... ................................................... ..................................... 9 1.8 ioram ................................................... ................................................... ................................... 9 1.9 flash ................................................... ................................................... .................................... 9 1.9.1 program se curity ................................................... ................................................... ....... 9 1.10 oscillator ................................................... ................................................... ................................ 9 1.11 pll and internal clock generation ................................................... ........................................... 9 1.12 real - time clock (rtc) ................................................... ................................................... ........ 10 1.13 hardware watchdog timer ................................................... ................................................... .. 10 1.14 temperature sensor ................................................... ................................................... ............ 10 1.15 general purpose digital i/o ................................................... ................................................... . 10 1.16 lcd drivers ................................................... ................................................... ......................... 11 1.17 eeprom interface ................................................... ................................................... .............. 11 1.18 spi slave port ................................................... ................................................... ...................... 11 1.19 test port ................................................... ................................................... ............................... 12 1.20 uarts ................................................... ................................................... .................................. 13 1.20.1 uart1 (opt_tx/opt_rx) ................................................... ....................................... 13 1.21 in circuit emulator (ice) port ................................................... ................................................. 13 2 electrical specifications ................................................... ................................................... ............. 14 2.1 absolute maximum ratings ................................................... ................................................... . 14 2.2 recommended external components ................................................... .................................... 15 2.3 recommended operating conditions ................................................... ..................................... 15 2.4 performance specifications ................................................... ................................................... . 16 2.4.1 input logic levels ................................................... ................................................... .... 16 2.4.2 output logic levels ................................................... ................................................... . 16 2.4.3 power - fault comparator ................................................... ............................................ 16 2.4.4 battery monitor ................................................... ................................................... ......... 17 2.4.5 supply current ................................................... ................................................... ......... 17 2.4.6 v3p3d switch ................................................... ................................................... .......... 17 2.4.7 2.5 v volt age regulator ................................................... ............................................. . 18 2.4.8 low - power voltage regulator ................................................... .................................... 18 2.4.9 crystal oscillator ................................................... ................................................... ...... 18 2.4.10 lcd dac ................................................... ................................................... ................. 18 2.4.11 lcd drivers ................................................... ................................................... ............. 19 2.4.12 optical interface ................................................... ................................................... ....... 19 2.4.13 temperature sensor ................................................... ................................................... 19 2.4.14 vref ................................................... ................................................... ....................... 20 2.4.15 adc converter, v3p3a referenced ................................................... .......................... 21 2.5 timing specifications ................................................... ................................................... ........... 22 2.5.1 flash memory ................................................... ................................................... .......... 22 2.5.2 eeprom interface ................................................... ................................................... .. 22 2.5.3 reset ................................................... ................................................... ..................... 22 2.5.4 rtc ................................................... ................................................... .......................... 22 2.5.5 spi slave port (mission mode) ................................................... ................................ 23 downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 3 3 packaging ................................................... ................................................... .................................... 24 3.1 68 - pin qfn package ................................................... ................................................... ........... 24 3.1.1 pinout ................................................... ................................................... ....................... 24 3.1.2 68 - pin qfn package outline ................................................... ..................................... 25 3.1.3 recommended pcb land pattern for the qfn - 68 package ........................................ 26 4 pin descriptions ................................................... ................................................... .......................... 27 4.1 power and ground pins ................................................... ................................................... ....... 27 4.2 analog pins ................................................... ................................................... .......................... 27 4.3 digital pins ................................................... ................................................... .......................... . 28 5 i/o equivalent circuits ................................................... ................................................... ................ 29 6 ordering information ................................................... ................................................... .................. 30 7 contact information ................................................... ................................................... .................... 30 8 appendix a: acronyms ................................................... ................................................... .............. 31 9 revision history ................................................... ................................................... .......................... 32 downloaded from: http:/// 78m6618 data sheet ds_6618_005 4 rev. 1. 4 figures figure 1: 78m6618 ic functional block diagram ................................................... ...................................... 6 figure 2: afe block diagram ................................................... ................................................... ................. 8 figure 3: spi slave port: typical read and write operations ................................................... ................ 12 figure 4: spi slave port (mission mode) timing ................................................... .................................. 23 figure 5: pinout for qfn - 68 package ................................................... ................................................... ... 24 figure 6: qfn - 68 package outline (top, bottom, and side view) ................................................... ......... 25 figure 7: pcb land pattern for qfn 68 package ................................................... ................................... 26 figure 8: i/o equivalent circuits ................................................... ................................................... ........... 29 tables table 1: spi comma nd description ................................................... ................................................... ...... 12 table 2: absolute maximum ratings ................................................... ................................................... .... 14 table 3: recommended external components ................................................... ....................................... 15 table 4: recommended operating conditions ................................................... ........................................ 15 table 5: input logic levels ................................................... ................................................... ................... 16 table 6: output logic levels ................................................... ................................................... ................ 16 table 7: power - fault comparator performance specifications ................................................... ............... 16 table 8: battery monitor performance specifications ( bme = 1) ................................................... ............. . 17 table 9: supply current performance specifications ................................................... .............................. 17 table 10: v3p3d switch performance specifications ................................................... ............................. 17 table 11: 2.5 v voltage regulator performance specifications ................................................... ............. . 18 table 12: low - power voltage regulator performance specifications ................................................... .... 18 table 13: crystal oscillator performance specifications ................................................... ......................... 18 table 14: lcd dac performance specifications ................................................... .................................... 18 table 15: lcd driver performance specifications ................................................... .................................. 19 table 16: optical interface performance specifications ................................................... .......................... 19 table 17: temperature sensor performance specifications ................................................... ................... 19 table 18: vref performance specifications ................................................... ........................................... 20 tabl e 19: adc converter performance specifications ................................................... ............................ 21 table 20: flash memory timing specifications ................................................... ....................................... 22 table 21: eeprom interface tim ing ................................................... ................................................... .... 22 table 22: reset timing ................................................... ................................................... ...................... 22 table 23: rtc range ................................................... ................................................... .......................... . 22 table 24 : spi slave port (mission mode) timing ................................................... ................................. 23 table 25: recommended pcb land pattern dimensions ................................................... ....................... 26 table 26: power and ground pins ................................................... ................................................... ........ 27 table 27: analog pins ................................................... ................................................... .......................... . 27 table 28: digital pins ................................................... ................................................... ............................ 28 table 29: ordering information ................................................... ................................................... ............. 30 downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 5 1 hardware functional description 1.1 hardware overview the teridian 78m6618 single - chip measurement and monitoring ic integrate s all the primary ac measurement and control blocks required to implement a n 8- outlet single - phase pdu with per outlet metering and intelligent relay control the 78m6618 includes: ? a ten - input a nalog front end (afe) ? an i ndependent digital computation engine (ce) ? an 8051 - compatible microprocessor (mpu) which executes one inst ruct ion per clock cycle (80515) ? a precision voltage reference ? a temperature sensor ? ram and flash memory ? a variety of i/o pi ns ? lcd drivers various current sensor technologies are supported including current transf ormers (ct), resistive shunts and rogowski coil s. in a sub - metering application, the 32 - bit compute engine (ce) of the 78m6618 sequentially process the samples from the analog inputs on pins ia, ib, ic, id, ie, if, ig, ih, va, vb and performs calculations to measure active energy (wh) and reactive energy (varh), as well as a 2 h and v 2 h for four - quadrant me asurement . these measurements are then accessed by the mpu, processed further, and output via the peripheral devices available to the mpu. in addition to the temperature - trimmed ultra - precisi on voltage reference, the on - chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of undesirable temperature effects on measure ment accuracy. temperature - dependent external com ponents such as a crystal oscillator and current sensor s can be characterized and their correction factors can be programmed to produce measurements with exceptional accuracy over the indus trial temperature range. a block diagram of the 78m6618 ic is shown in figure 1 . a detailed description of the various functional blocks follows . downloaded from: http:/// 78m6618 data sheet ds_6618_005 6 rev. 1. 4 ? adc converter vref muxp xin xout vref reset v1 uart tx rx com1, 0 lcd display driver digital i/o power fault gndd v3p3a v3p3d vbat volt reg 2.5v to logic v2p5 tmuxout faultz gnda vbias temp osc (32.768khz) mck pll vref test test mode e_rxtx rtc vbias ice_e v3p3sys test mux vbat ce_prog ck_ce ck_mpu 80mhz vadc ce multi- purpose io rtm rpulse wpulse com0, com1 seg0... dio_4... to tmux spi slave eeprom i/f flash 128kb xram 4kb ce_data pcsz pclk psdi psdo sdata sclk sfr 80515 mpu emulator e_tclk e_rstz seg7 seg8 seg9 / e_rxtx seg10 / e_tclk seg11 / e_rst seg12 seg14 seg16 seg15 seg17 dio4 / seg24 dio5 / seg25 dio6 / seg26 dio7 / seg27 dio10 / seg30 rpulse wpulse xram bus 8 16 32 cktest ice_e cktesti seg0 seg1 seg2 seg3 / pclk seg4 / psdo seg5 / pcsz seg6 / psdi fir ih va vb ig xpulseypulse xpulse ypulse dio8 / seg28 dio9 / seg29 seg18 seg19 dio43 / seg63 dio18 / seg38 dio17 / seg37 dio13 / seg33 dio14 / seg34 dio15 / seg35 dio16 / seg36 id ie if ic ia ib opt_rx / dio1 opt_tx / dio2 optical mod dio3 dio11 / seg31 dio19 / seg39 figure 1 : 78m6618 ic functional block diagram downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 7 1.2 device reset when the reset pin is pulled hig h, all digital activity stops. only the oscillator and rtc module continue to run. additionally, all io ram bits are set to their default states. as long as v1 ( the input voltage at the power fault block) is greater than vbias, the internal 2.5 v regulator will continue to provide power to the digital section. once initiated, the reset mode will persist until the reset timer tim es out. this will occur in 4 096 cycles of the crystal clock after reset goes low, at which time the mpu will begin execut ing its preboot and boot sequences from address 0x00 00 . 1.3 power management 1.3.1 voltage regulator the 78m6618 provides an on chip voltage regulator to create a 2.5v supply for the digital l ogic. this regulator can be run off of the v3p3sys or vbat inputs depending upon power availabili ty. 1.3.2 power fault management the 78m6618 include s both hardware and software controlled power fault management. v1 is connected to a comparator to monitor system power fault conditions. when the output of the c omparator falls (v1 ds_6618_005 78m6618 data sheet rev. 1. 4 9 1.6.1 sfr several custom special function registers (sfr) registers are implem ented in the 78m6618 s 80515 mpu. see the 78m6618 programmers reference manual for more information regarding the mapping of functionality to specific sfr and ioram addresses. 1.7 xram the ce and mpu share a single , general purpose 4 k b ram (also referred to as xram) for data . the xram is natively accessible as 32bit words from the ce and on 8 bit boundar ies from the cpu. the xram is accessed by the cpu through addresses 0x0000 to 0x0fff. 1.8 io ram the mpu accesses most of its external input and output functionality as w ell as programmable functionality through memory mapped io (ioram). the ioram is access ed by the cpu as data addresses 0x2000 to 0x20ff. see the 78m6618 programmers reference manual for more information regarding the mapping of functionality to specific ioram addresses. 1.9 flash the 78m6618 includes 128 kb of on - chip f lash memory. for re ad/write access from the cpu, t he flash is broken into four 32 kb banks that are managed by sfr settings. for erasing of the flash memo ry from the cpu the flash is segmented into individual 1024 - byte pages and also controlled by sfr settings. see the 78m6618 programmers reference manual for more information regarding the use of flash and the mapping of functionality to specific sfr settings. 1.9.1 program security the 78m6618 has functionality to guarantee the security of the users mpu and ce program code . when enabled, the security feature limits the ice to global flash erase operations only. all other ice operations are blocked. security is enabled by mpu code that is executed in a pre - boot interval before the primary boot sequence begins. once security is enabled, the only way t o disable it is to perform a global erase of the flash , followed by a chip reset. 1.10 oscillator the 78m6618 oscillator drives a standard 32.768 khz watch crystal . these crystals are accurate and do not require a high - current os cillator circuit . the 78m6618 oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited powe r handling capability. the oscillator is powered directly and only from the vbat pin , which therefore must be connected to a dc voltage source not to exceed 4 v . the oscillator requires approximately 100 na, which is negligible compared to the internal leakage of a battery since the oscillator is self - biasing, an external resistor must not be conn ected across the crystal. 1.11 pll and internal clock generation timing for the device is derived from the 32.768 khz crystal oscillator output . the pll and o n- chip timing functions provide several clocks which include : ? t he mpu clock (ckmpu) ? t he emulator cl ock (2 x ckmpu) ? t he clock for the ce (ckce) ? t he delta - sigma adc and fir clock (ckadc, ckfi r) these internal clocks can be adjusted for various programmable rates which af fect device functionality. see the 78m6618 programmers reference manual for more info rmation regarding the prog rammability of the 78m6618 pll and internal clock generation modules . downloaded from: http:/// 78m6618 data sheet ds_6618_005 10 rev. 1. 4 v3p3 v3p3 - 400mv v3p3 - 10mv vbias 0v battery modes normal operation, wdt enabled wdt dis- abled v1 1.12 real - time clock (rtc) the rtc circuit is driven directly by the crystal oscillator . the rtc consists of a counter chain and output registers . the counter chai n consists of registers for seconds, minutes, hours, day of week, day of month, month , and year (including leap years ). see the 78m6618 programmers reference manual for more information regarding the use of the 78m6618 rtc. 1.13 hardware watchdog timer in addition to the basic watchdog timer included in the 80515 mpu, an independent, robust, fixed - duration, watchdog timer (wdt) is included in the device. it uses the crystal oscillator as its time base and must be refreshed by the mpu firmware at least every 1.5 seconds. when not refreshed on time the wdt overflows, and the part is reset as if the rese t pin were pulled high, except that the ioram bits will be maintained. 4096 oscillator cycles (or 125 ms) after the wdt overflow, the mpu wil l be launched from program address 0x0000. asserting ice_e will deactivate the wdt. the wdt can also be disabled by tying the v1 pin to v3p3. t his also deactivates v1 power fault detection. since there is no method in firmware to disable the crystal oscillator or the wdt, it is guaranteed that whatever state the part might find itself in, upon watchdog overflow, the part will be reset to a known state. figure 3 : functions defined by v1 1.14 temperature sensor the device includes an on - chip temperature sensor for determining the temperature of the bandgap re - ference. the primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system . see the 78m6618 programmers reference manual for more information regarding the use of the 78m6618 temperature sensor. 1.15 general purpose digital i/o the 78m6618 in cludes up to 19 pins of general - purpose digital i/o. when configured as inputs, these pins are 5v compatible (no cur rent - limiting resistors are needed). on reset or power - up, all dio pins are inputs until they are configured for the desired direction under mpu control . the digital i/o pins can be categorized as follows: ? dio1/opt_rx, dio2/opt_tx (2 pins) uart/dio pin ? dio3 (1 pin ) dedicated dio pin ? dio4/seg24 -- dio1 1 /seg 31 (8 pins) lcd/dio pins ? dio13/seg33 -- dio 1 9/seg 3 9 (7 pins) lcd/dio pins ? dio43/seg63 (1 pin ) lcd/dio pin downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 11 1.16 lcd drivers the 78m6618 contains a total of 3 5 dedicated and multiplexed lcd drivers which are grouped as follows: ? 11 dedicated lcd segment drivers . ? 3 drivers multiplexed with the ice interface (e_tclk, e_rst, e_rxtx) . ? 1 driver multiplexed with auxiliary signal cktest ( seg19) . ? 4 drivers multiplexed with the spi port (pclk, psdo, pcsz, psdi) . ? 16 drivers multiplexed with general purpose dio pins . ? 2 common drivers for multiplexing (50%, or 100% duty cycle) C always available . with a minimum of 15 driver pins always available and a total of 3 5 driver pins in the maximum con - figuration, the device is capable of driving between 30 to 70 pixels of lcd display. at eight pixels per digit, this corresponds to 3 to 8 digits . the following dedicated and multi - use pins can be assigned as lcd segment pins for the 78m6618: ? 11 dedicated lcd segment pins: seg0 to seg2, seg7, seg8, seg12, seg14 to s eg18. ? 8 dual - function pins: seg3/pclk, seg4/psdo, seg5/pcsz, seg6/psdi, e_rxtx/seg9, e_tclk/seg10, e_rst/seg11, and seg19/cktest. ? 16 combined dio and segment pins: seg24/dio4 to seg31/dio11, seg33/dio13 to seg39/dio19, and seg63/dio43. of which, dio7/seg27 through dio15/seg35 can be used for controlling relays. see the 78m6618 programmers reference manual for more information regarding the programmability of the 78m6618 lcd drivers. see the 78m6618 hardware design guidelines for more information regarding connecting the 78m6618 lcd drivers to lcds. 1.17 eeprom interface the 78m6618 provide s hardware support for a n optional two - pin or a three - wire ( - wire) eeprom interfa ce. two - pin eeprom interface the dedicated 2 - pin serial interface communicates with external eeprom devices . the interface is multiplexed onto the dio4 (sck) and dio5 (sda) pins . three- wire ( - wire) eeprom interface a 500 khz three - wire interface, using sdata, sck and a dio pin for cs is also available . see the 78m6618 programmers reference manual for more information regarding the programmability of the 78m6618 eeprom interfaces. see the 78m6618 hardwa re design guidelines for more information regarding connecting the 78m6618 eeprom interfaces to various eeprom. 1.18 spi slave port the slave spi port communicates directly with the mpu data bus and is abl e to directly read and write x ram and io ram locations . it is also able to send commands to the mpu . the interface to the slave port consists of the pcsz, pclk, psdi and psdo pins . these pins are multiplexed with the lcd segment driver pins seg3 to seg6 . a typical spi transaction is as follows . while pcsz is high, the port is held in an initialized/reset state . during this state, psdo is held in hiz state and all transitions on pclk and psdi are ignored . when pcsz falls, the port will begin the transaction on the first rising edg e of pclk . a transaction consists of an 8 - bit command, a 16 - bit address and then one or more bytes of data . the transaction ends when pcsz is raised. some transactions may consist of a command only . the last spi command and a ddress (if part of the command) are available in the ioram. downloaded from: http:/// 78m6618 data sheet ds_6618_005 12 rev. 1. 4 the spi port supports data transfers at up to 1 mb/s . the spi commands are described in table 1 and figure 4 illustrate s the spi interface read and write timing. table 1 : spi command description co mmand description 11xx xxxx addr d0 ... d n output data on psdo is read from ram starting with byte at addr. addr will auto - increment until pcsz is raised. mpu spi interrupt is generated 1100 0000 addr d0 ... d n output data on psdo is read from ram starti ng with byte at addr. addr will auto - increment until pcsz is raised. no mpu spi interrupt is generated 10 xx xxxx addr d0 ... d n input data on psdi is written to ram starting with byte at addr. addr will auto - increment until pcsz is raised. mpu spi interr upt is generated 10 00 0000 addr d0 ... d n input data on psdi is written to ram starting with byte at addr. addr will auto - increment until pcsz is raised. no mpu spi interrupt is generated cmd addr d0 ... d n cmd and addr are available to the cpu in ioram d0 dn are ignored. mpu spi interrupt is generated a15 a14 a1 a0 c0 0 31 x d7 d6 d1 d0 d7 d6 d1 d0 c5 c6 c7 x pcsz psck psdi psdo 8 bit cmd 16 bit address data[addr] data[addr+1] 7 8 23 24 32 39 extended read . . . serial read a15 a14 a1 a0 c0 0 31 c5 c6 c7 x pcsz psck psdi psdo 8 bit cmd 16 bit address data[addr] data[addr+1] 7 8 23 24 32 39 extended write . . . serial write d7 d6 d1 d0 d7 d6 d1 d0 x hi z hi z (from host) (from 6531) (from host) (from 6531) figure 4 : spi slave port : typical r ead and w rite operations since the addresses are in 16 - bit format, any type of xram data can be accessed: ce, mpu or ioram but not sfrs or the 80515 - internal register bank. see the 78m6618 programmers reference manual for more information regarding the mapping and use of spi functions. 1.19 test port one out of 16 digital or 8 analog signals can be selected to be output on the tmuxout pin. see the 78m6618 programmers reference manual for more information regarding the use of tmuxout. downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 13 1.20 uarts the 78m 6618 includes two uart s (uart0 and uart1) that can be programmed to communicate with a variety of external device s. the uart s are dedicated 2 - wire serial interface s , which can communicate at rates up to 38,400 bits/s. all uart transfers are pro grammable for parity enable, parity, 2 stop bits/1 stop bit and xon/xoff options for variable communication baud rates from 300 to 38,400 bps. see the 78m6618 programmers reference manual for more information regarding the use of the uart resources. 1.20.1 uart1 (opt_tx/opt_rx) the device includes an interface to implement an ir/optical port on uart1. the pin opt_tx is designed to directly drive an external led for transmitting data on an optical link. the pin opt_rx has the same threshold as the rx (uart0) pin, but can also be used to sense the input from an external photo detector used as the receiver for the optical link. alt ernately, the uart1 may be interfaced with a standard level uart transceiver. contact teridian support for more informat ion. 1.21 in circuit emulator (ice) port the 78m6618 implements an in circuit emulator(ice) port for debug and programming of th e device. to enable the use of the port the ice_e pin must be pulled high. in this mode the seg11,se g10 and seg9 pins are repurposed and the e_rst, e_tclk and e_rxtx pins respectively. please contact teridian support for more information regarding the use of the ice interface for device p rogramming and debug. downloaded from: http:/// 78m6618 data sheet ds_6618_005 14 rev. 1. 4 2 e lectrical s pecifications 2.1 a bsolute m aximum r atings table 2 shows the absolute maximum ranges for the device. stresses beyond absol ute maximum ratings may cause permanent damage to the device. these are stress ratings o nly and functional operation at these or any other conditions beyond those indicated under recommended operat ing conditions ( section 4.3 ) is not implied. exposure to absolute - maximum - rated conditions for extend ed periods may affect device reliability. all voltages are with respect to gnda. table 2 : absolute maximum ratings voltage and current supplies and ground pins v3p3sys, v3p3a - 0.5 v to 4.6 v vbat - 0.5 v to 4.6 v gndd - 0.5 v to +0.5 v analog output pins v3p3d - 10 ma to 10 ma, - 0.5 v to 4.6 v vref - 10 ma to +10 ma, - 0.5 v to v3p3a+0.5 v v2p5 - 10 ma to +10 ma, - 0.5 v to 3.0 v analog input pins ia, ib, ic, id, ie, if, ig, ih, va , vb, v1 - 10 ma to +10 ma - 0.5 v to v3p3 a+0.5 v xin, xout - 10 ma to +10 ma - 0.5 v to 3.0 v all other pins configured as seg or com drivers -1 ma to +1 ma, - 0.5 to v3p3d+0.5 configured as digital inputs - 10 ma to +10 ma, - 0.5 to 6 v configured as digital outputs - 15 ma to +15 ma, - 0.5 v to v3p3d+0.5 v all other pins - 0.5 v to v3p3d+0.5 v temperature and esd stress operating junction temp erature (peak, 100ms) + 140c operating junction temperature (continuous) + 125c storage t emperature range - 45 c to +165 c lead temperature (soldering, 10s) +300 c solder ing t emperature (reflow) +260 c esd s tress on all pi ns 4 kv downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 15 2.2 recommended external components table 3 : recommended external components name from to function value unit c1 v3p3a agnd bypass capa citor for 3.3 v supply 0.1 20% f c2 v3p3d dgnd bypass capacitor for 3.3 v output 0.1 20% f csys v3p3sys dgnd bypass capacitor for v3p3sys 1.0 30% f c2p5 v2p5 dgnd bypass cap acitor for v2p5 0.1 20% f xtal xin xout 32.768 khz crystal C electrically similar to ecs .327 - 12.5 - 17x or vishay xt26t, load capacitance 12.5 pf . 32.768 khz cxs xin agnd load capacitor for crystal (depends on crystal specs and b oard parasitics). 33 10% pf cxl xout agnd load capacitor for crystal (depends on crystal specs and board parasitics). 15 10% pf notes: 1. agnd and dgnd should be connected together. 2. v3p3sys and v3p3a should be connected together. 2.3 r ecommended operating c onditions table 4 : recommended operating conditions p arameter condition min typ max unit v3p3sys, v3p3a : 3.3 v supply voltage v3p3a and v3p3sys must be at the same voltage normal operation 3.0 3.3 3.6 v battery backup 0 3.6 v vbat no battery externally connect to v3p3sys battery backup : brn and lcd modes sleep mode 3.0 2.0 3.8 3.8 v v operating temperature - 40 +85 oc downloaded from: http:/// 78m6618 data sheet ds_6618_005 16 rev. 1. 4 2.4 p erformance s pecifications 2.4.1 input logic levels table 5 : input logic level s p arameter condition m in t yp m ax u nit digital high - level input voltage a , v ih 2 v digital low - level input voltage a , v il 0.8 v input pull - up current, i il e_rxtx, e_rst, cktest other digital inputs vin=0 v, ice_e=1 10 10 -1 0 100 100 1 a a a input pull down current, i ih ice_e reset other digital inputs vin = v3p3d 10 10 -1 0 100 100 1 a a a a in battery powered modes, digital inputs should be below 0.3 v or above 2.5 v to minimize battery current. 2.4.2 o utput logic levels table 6 : output logic levels p arameter condition m in t yp m ax u nit digital high - level output voltage v oh i load = 1 ma v3p3d C 0.4 v i load = 15 ma v3p3d - 0.6 v digital low - level output voltage v ol i load = 1 ma 0 0.4 v i load = 15 ma 0.8 v opt_tx v oh ( v3p3d -opt_tx) i source =1 ma 0.4 v opt_tx v ol i sink =20 ma 0.7 v 2.4.3 power - fault c omparato r table 7 : power - fault comparator performance specifications p arameter condition m in t yp m ax u nit offset voltage : v1 - vbias - 20 +15 mv hysteresis current: v1 vin = vbias C 100 mv 0.8 1.2 a response tim e : v1 + 100 mv overdrive voltage at v1 rising voltage at v1 falling 10 8 37 100 100 s s wdt disable threshold: v1 - v3p3a - 400 - 10 mv downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 17 2.4.4 battery monitor table 8 : battery monitor performance specifications ( bme = 1) p arameter condition m in typ max unit load resistor 27 45 63 k lsb value [ m40mhz , m26mhz ] = [00], [10], or [11] fir_len =0 (l=138) fir_len =1 (l=288) (- 10%) - 48.7 - 5.35 (+10%) v v [ m40mhz , m26mhz ] = [01] fir_len =0 (l=186) fir_len =1 (l=384) (- 10%) - 19.8 - 2.26 (+10% ) v v offset error - 200 0 +100 mv 2.4.5 s upply c urrent table 9 : supply current performance specifications p arameter condition m in t yp max unit v3p3sys current (ce off) normal operatio n, v3p3a = v3p3sys = 3.3 v ckmpu = 614 khz no flash memory write rtm_e =0, eck_dis =1, adc_e =1, ice_e =0 4.2 6 .3 5 ma v3p3sys current (ce on) 8.4 9.6 ma v3p3a current 3. 3 3.8 ma vbat current - 400 +400 na v3p3sys current, write flash normal operation as above, except write flash at maximum rate, ce_e = 0, adc_ e = 0 9.1 12 ma vbat current vbat=3.6 v brownout mode lcd mode, lcd dac off < 25c over temperature lcd mode, lcd dac on < 25c over temperature sleep mode, 25c sleep mode , over temperature 52 11 15 16 21 0.5 0.7 250 20 30 25 35 1 1.5 a a a a a a a 2.4.6 v3p3d s witch table 10 : v3p3d switch performance specifications p arameter condition m in t yp max unit on resistance C v3p3sys to v3p3d | i v3p3d | 1 ma 9 15 on resistance C vbat to v3p3d | i v3p3d | 1 ma 32 50 downloaded from: http:/// 78m6618 data sheet ds_6618_005 18 rev. 1. 4 2.4.7 2.5 v v oltage r egulator table 11 : 2.5 v voltage regulator performance specifications p arameter condition m in t yp max unit v2p5 i load = 0 2.3 2.5 2.7 v v2p5 load regulation i load = 0 ma to 5 ma 40 mv voltage overhead v3p3 - v2p5 i load = 5 ma, r educe v3p3 until v2p5 drops 200 mv 470 mv pssr ? v2p5/ ? v3p3 reset=0, iload=0 -2 +2 mv/v 2.4.8 l ow -p ower v oltage r egulator unless otherwise specified, v3p3sys = v3p3a = 0. table 12 : low - power voltage regulator performance specifications p arameter condition m in t yp max unit v2p5 i load = 0 2. 3 2.5 2.7 v v2p5 load regulation i load = 0 ma to 1 ma 30 mv vbat voltage requirement i load = 1 ma, r educe vbat until reg_lp_ok = 0 3.0 v psrr v2p5/vbat i load = 0 - 50 50 mv/v 2.4.9 c rystal o scillator table 13 : crystal oscillator performance specifications p arameter condition m in t yp max unit maximum output power to crystal 4 crystal connected 1 w xin to xout capacitance 1 3 pf capacitance to d gnd 1 xin xout rtca_adj = 0 5 5 pf pf 2.4.10 lcd dac table 14 : lcd dac performance specifications p arameter condition m in t yp max unit vlcd voltage v 019 .0 lcd_dac) 059 .0 1(3p3v v lcd ? ? ? ? = 1 lcd_dac 7 - 10 +10 % downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 19 2.4.11 lcd d rivers the information in table 15 a pplies to all com and seg pins with lcd_dac [2:0] = 000 . table 15 : lcd driver performance specifications p arameter condition m in t yp max unit vlc2 voltage with respect to vlcd 1 - 0.1 +0 .1 v vlc0 voltage, ? bias with respect to vlc2/2 -4 +1 % vlc0 impedance ? i load = 100 a ( isink) 9 15 k ? i load = - 100 a ( isource) 9 15 1 vlcd is v3p3sys in mission mode and vbat in brownout and lcd modes. 2.4.12 optical interface table 16 : optical interface performance specifications p arameter condition m in t yp max unit opt_tx v oh (v3p3d -opt_tx) i source = 1 ma 0.4 v opt_tx v ol i sink = 20 ma 0.7 v 2.4.13 temperature s ensor table 17 shows the performance for the temperature sensor . the lsb values do not include the 8- bit left shift at ce input. table 17 : temperature sensor performance specifications p arameter condition m in t yp max unit nominal relationship: n(t) = s n * (t -t n ) + n n , t n = 25oc nominal sensitivity (s n ) 3 n 3 l 00107 .0 s ?? ? ?? ? ? ?= [ m26 mhz , m40 mh ] = [00], [ 0 1], or [11] fir_len =0 (l=138) fir_len =1 (l=288) - 104 - 947 lsb/oc [ m26 mhz , m 40 mhz ] = [1 0] fir_len =0 (l=186) - 255 nominal offset (n n ) 4 3 n 3 l 510 .0 n ?? ? ?? ? ? = [ m26 mhz , m40mh ] = [00], [ 0 1], or [11] fir_len =0 (l=138) fir_len =1 (l=288) 49641 451200 lsb [ m26 mhz , m 40 mhz ] = [1 0] fir_len =0 (l=186) 121500 temperature error 2 ? ? ? ? ? ? + ? ? = n n n t s n tn t err ) )(( t n = 25c , t = - 40oc to +85oc - 10 1 10 1 oc 1 guaranteed by design ; not production tested. 2 n n is measured at t n during measurement calibration and is stored in mpu or ce for use in temperature calculations. downloaded from: http:/// 78m6618 data sheet ds_6618_005 20 rev. 1. 4 2.4.14 vref table 18 shows the performance specificat i ons for vref . unless otherwise specified, vref_dis = 0. table 18 : vref performance specifications p arameter condition m in t yp max unit vref output voltage, vref(22 ) ta = 22oc 1.193 1.195 1.197 v vref chop step 40 mv vref power supp ly sensitivity vref / v3p3a v3p3a = 3.0 to 3.6 v - 1.5 1.5 mv/v vref input impedance vref_dis = 1 , vref = 1.3 to 1.7 v 100 k vref output impedance cal =1, i load = 10 a, - 10 a 2.5 k vnom de finition 2 2 )22 ( 1 )22 ()22( )( 2 tc t tc t vref t vnom ? + ? + = v vnom temperature coefficients : tc1 tc2 3.18 (52.46 - trimt ) - 0.4 44 v /oc v /c 2 vref(t) deviation from vnom(t) )40,22 max( 10 )( )( )( 6 ? ? t t vnom t vnom t vref - 40 1 +40 1 ppm/oc vref aging 25 ppm/ year 1 guaranteed by design ; not production tested. 2 this relationship describes the nominal behavior of vref at different temperat ures. downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 21 2.4.15 adc converter , v3p3a re ferenced table 19 shows the performance specifications for the adc converter, v3p3a ref erenced. for this data, fir_len =0, vref_dis =0 and lsb values do not include the 9 - bit left shift at the ce input. tab le 19 : adc converter performance specifications p arameter condition m in t yp max unit recommended input range (vin - v3p3a ) - 250 250 mv peak voltage to current crosstalk ) cos( * 10 6 vcrosstalk vin vin vcrosstalk ? vin = 200 mv peak, 65 hz, on va . vcr osstalk = largest measurement on ia or ib - 10 1 10 1 v/v thd (first 10 harmonics) 1 : 250 mv - pk 20 mv - pk vin=65 hz, 64 kpts fft, blackman - harris window ckce = 5 mhz - 75 - 90 db db input impedance vin = 65 hz 40 90 k tempera ture coefficient of input impedance vin = 65 hz 1.7 /c lsb size 3 3 75.4 25.1 ?? ? ?? ? ? ? = l v v ref lsb l = fir length [ m40mhz , m26mhz ] = [00], [10], or [11] fir_len =0 fir_len =1 3231 355 nv/ lsb [ m40mhz , m26mhz ] = [01] fir_len =0 1319 nv/ lsb digital full scal e 3 3 ?? ? ?? ? l l = fir length [ m40mhz , m26mhz ] = [00], [10], or [11] fir_len =0 fir_len =1 97336 884736 lsb [ m40mhz , m26mhz ] = [01] fir_len =0 238328 lsb a dc gain error versus %power supply variation 3.3/3 3 100 / 357 10 6 a p v v nv nout in pk ? ? vin=200 mv pk, 65 hz v3p3a=3.0 v, 3.6 v 50 ppm/% input offset (vin - v3p3a ) - 10 10 mv 1 guaranteed by design ; not production tested. downloaded from: http:/// 78m6618 data sheet ds_6618_005 22 rev. 1. 4 2.5 t iming s pecifications 2.5.1 flash memory table 20 : flash memor y timing specifications p arameter condition m in t yp max unit flash write cycles - 40c to +85c 20,000 cycles flash data retention 25c 100 years flash data retention 85c 10 years flash byte write operations between page or mass erase operations 2 cycles write time per byte 42 s page erase (1024 bytes) 20 ms mass erase 200 ms 2.5.2 eeprom i nterface table 21 : eeprom interface timing p arameter condition m in t yp max unit write clock frequency (i 2 c) ckmpu = 4.9152 mhz , using interrupts 78 khz ckmpu = 4.9 152 mhz, bit - banging dio4/5 150 khz write clock frequency (3 - wire) ckmpu = 4.9152 mhz 500 khz 2.5.3 reset table 22 : reset timing p arameter condition m in t yp max unit reset pulse width 5 s reset pulse fall time 1 1 s 1 guaranteed by design ; not production tested. 2.5.4 rtc table 23 : rtc range p arameter condition m in t yp max unit range for date 2000 2255 year downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 23 2.5.5 spi slave p ort ( miss ion m ode) table 24 : spi slave port (mission mode) timing p arameter condition m in t yp max unit t spicyc pclk cycle time 1 s t spilead enable lead time 15 ns t spilag enable lag time 0 ns t spiw pclk pulse width : high low 40 40 ns ns t spisck pcsz to first pclk fall ignore if pclk is low when pcsz falls. 2 ns t spidis disable time 0 ns t spiev pclk to data out 15 ns t spisu data input setup time 10 ns t spih data input hold time 5 ns msb out lsb out msb in lsb in t spicyc t spilead t spilag t spisck t spih t spiw t spiev t spiw t spidis pcsz pclk psdi psdo figure 5 : spi slave port ( mission mode ) timing downloaded from: http:/// 78m6618 data sheet ds_6618_005 24 rev. 1. 4 3 p ackag ing 3.1 68 - pin qfn package 3.1.1 pinout 1 teridian 78m6618-im 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 32 26 27 28 29 30 18 19 20 21 22 24 25 35 36 37 38 39 40 41 42 43 44 45 46 47 48 6463 62 61 6752 53 54 55 56 57 58 59 60 65 66 seg9/ e_rxtx gndd tmuxout e_rst/seg11 tx seg3/ pclk v3p3d seg19/ cktest seg4/ psdo seg5/ pcsz opt_tx/dio2 v3p3sys seg37/dio17seg38/dio18 com0 dio3 seg17 seg16 seg15 seg7seg8 seg6/ psdi seg36/dio16 seg35/dio15 seg34/dio14 seg2 seg1 com1 seg0 seg63/dio43 seg14 seg12 v3p3aseg27/dio7/ rpulse seg26/dio6/ wpulse seg25/dio5/ sdata seg29/dio9/ ypulse rx seg31/dio11 resetv2p5 vbat seg24/dio4/ sdck seg28/dio8/ xpulse ice_eseg18 seg39/dio19 seg30/dio10 testie ig xinif gnddopt_rx/dio1 vref ia ib ic id vavb ih v1 17 e_tclk/seg10 23 seg33/dio13 3334 49 50 gnda 51 68 xout figure 6 : pinout for qfn - 68 packa ge downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 25 3.1.2 68 - pin qfn package outline figure 7 : qfn - 68 package outline ( top , bottom, and side view ) note: controlling dimensions are in mm pin length is nominally 0.4mm (min. 0.3 mm, max 0.4 mm). 0.85 0 downloaded from: http:/// 78m6618 data sheet ds_6618_005 26 rev. 1. 4 3.1.3 recommended pcb land pattern for the qfn - 68 package figure 8 : pcb land pattern for qfn 68 package table 25 : recommended pcb land pattern dimensions symbol description typical dimension e lead pitch 0.4 mm x pad width 0.23 mm y p ad length. nee note 3 . 0.8 mm d see note 1 6.3 mm a 6.63 mm g 7.2 mm notes: 1. do not place unmasked vias in the region denoted by dimension d. 2. soldering of bottom internal pad is not required for proper operation. 3. the y dimension has been elongated to allow for hand soldering and reworking. p roduction assembly may allow this dimension to be reduced as long as the g dimension is maintained. downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 27 4 pin d escriptions 4.1 power and ground pins table 26 : power and ground pins name type circuit description gnda p C analog ground: this pin should be connected directly to the ground plane. gndd p C digital ground: this pin should be connected directly to the ground plane. v3p3a p C analog power supply: a 3.3 v power supply should be connected to this pin, must be the same voltage as v3p3sys. v3p3sys p C system 3.3 v supply. this pin should be connected to a 3.3 v power supply. v3p3d o 13 auxiliary voltage output of the chip, controlled by the internal 3.3 v selection switch . in mission mode, this pin is internally connected to v3p3sys . in brownout mode, it is internally connected to vbat . this pin is left unconnected in lcd and sleep mode. a bypass capacitor to ground should not exceed 0.1 f. vbat p 12 battery backup and oscillator power supply . a battery or super - capacitor is to be connected between vbat and gndd . if no battery is used, connect vbat to v3p3sys. v2p5 o 10 output of the internal 2.5 v regulator . leave this pin open . 4.2 analog pins t able 27 : analog pins name type circuit description ia, ib , ic, id, ie, if, ig, ih i 6 line current sense inputs: these pins are voltage inputs to the internal a/d converter . typically, they are connected to the outputs of current sensors . unused pins must be tied to v3p3a . va, vb i 6 line voltage sense inputs: these pins are voltage inputs to the internal a/d converter . typically, they are connected to the outputs of resistor dividers . unused pins must be tied to v3p3a. v1 i 7 comparator input: this pin is a voltage input to the internal comparator . the voltage applied to the pin is compared to the internal bias voltage (1.6 v) . if the input voltage is above vbias, the comparator output will be high (1) . if the comparator output is low, a voltage fault will occur . a series 5 k ? resistor should be connected from v1 to the resistor divider. vref o 9 voltage reference for the adc . normally disabled and left unconnected . if en abled, a 0.1 f capacit or to v3p3 a should be connected to this pin. xin xout i 8 crystal inputs: a 32 khz crystal should be connected across these pins . typically, a 33 pf capacitor is also connected from xin to gnda and a 15 pf capacitor is connected from xout to gnda . it is important to mi - nimize the capacitance between these pins . see the crystal manufacturer datasheet for details. if an external clock is used, a 150 mv (p - p) clock signal should be applied to xin, and xout should be left unconnected. 1) pin types: p = power, o = output, i = input, i/o = input/output the circuit number denotes the equivalent circuit, as specified under section 5 , i/o equivalent circuits . downloaded from: http:/// 78m6618 data sheet ds_6618_005 28 rev. 1. 4 4.3 digital pins table 28 : digital pins name type circuit description com1, com0 o 5 lcd common outputs: these 2 pins provide the select signals for an lcd display. dio3 i/o 3,4 dedicated dio pin. seg0seg2, seg7, seg8 seg12, seg14 seg18 o 5 dedicated lcd segment output pins. seg24/dio4 seg3 1 /dio1 1, seg 33 /dio 13 seg3 9 /dio1 9, seg63/dio43 i/o 3, 4, 5 multi - use pins, c onfigurable as either lcd seg driver or dio. (dio4 = sck, dio5 = sda when configured as eeprom interface; wp ulse = dio6, varpulse = dio7 when configured as pulse outputs). if unused, these pins must be configured as dios and set to outputs by the firmware . seg3/pclk seg4/psdo seg5/pcsz seg6/psdi i/o 3, 4, 5 multi - use pins, configurable as either lcd seg drive r or spi port. e_rxtx/seg9 i/o 1, 4, 5 multi - use pins, configurable as either emulator port pins (when ice_e pulled high) or lcd seg drivers (when ice_e tied to gnd). e_rst/seg11 i/o 1, 4, 5 e_tclk/seg10 o 4, 5 ice_e i 2 ice enable. when zero, e_rst , e_tclk and e_rxtx become seg32, seg33 and seg38 respectively. for production units, this pin should be pulled to gnd to disable the emulator port. cktest/seg19 , muxsync/seg7 o 4, 5 multi - use pin s , configurable as either multiplexer/clock output or lcd s egment driver using the i/o ram registers ckout_e or mux_sync_e. tmuxout o 4 digital output test multiplexer. controlled by t mux[3:0]. opt_rx/dio1 i/o 3, 4, 7 multi - use pin, configurable as optical receive input or general dio. when configured as opt_r x, this pin receives a signal from an external photo - detector used in an ir serial interface . if unused, this pin must be terminated to v3p3d or gndd, or configured as a dio and set to an output by the firmware . opt_tx/dio2 i/o 3, 4 multi -u se pin, configurable as either optical led transmit o utput, wpulse, rpulse, or general dio. when configured as opt_tx, this pin is capable of directly driving an led for transmitting data in an ir serial interface. if unused, this pin must be left open, or configured as a dio and set to an output by the firmware . reset i 2 chip reset: this input pin is used to reset the chip into a known state. for normal operation, this pin is pulled low. to reset the chip, this pin should be pulled high. this pin has an internal 30 a (nominal) current source pull - down. no external reset circuitry is necessary. rx i 3 uart input. if this pin is unused , it must be terminated to v3p3d or gndd. tx o 4 uart output. test i 7 enables production test. this pin must be grounded in normal operation. pin types: p = power, o = output, i = input, i/o = inp ut/output. the circuit number denotes the equivalent circuit, as specified in section 5 i/o equivalent ci rcuits . downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 29 5 i/o equivalent circuits figure 9 : i/o equivalent circuits oscillator equivalen t circuit type 8: oscillator i/o v3p3d digital input pin digital input equivalent circuit type 1: standard digital input or pin configured as dio input with internal pull - up gndd 110k v3p3d cmos input digital input pin digital input type 2: pin configured as dio input with internal pull - down gndd 110k gndd cmos input v3p3d digital input type 3: standard digital input or pin configured as dio input gndd cmos input v3p3d digital input pin cmos output gndd v3p3d gnd d v3p3d digital output equivalent circuit type 4: standard digital output or pin configured as dio output digital output pin lcd output equivalent circuit type 5: lcd seg or pin configured as lcd seg lcd driver gndd lcd seg output pin to mux gnda v3p3a analog input equivalent circuit type 6 : adc input analog input pin comparator input equivalent circuit type 7: comparator input gnda v3p3a to comparator comparator input pin to oscillator gndd oscillator pin vref equivalent circuit type 9: vref from internal reference gnda v3p3a vref pin v2p5 equivalent circuit type 10: v2p5 from internal reference gndd v3p3d v2p5 pin vlcd equivalent circuit type 11: vlcd power gndd lcd drivers vlcd pin vbat equivalent circuit type 12: vbat power gndd power down circuits vbat pin v3p3d equivalent circuit type 13: v3p3d from v3p3sys v3p3d pin from vbat 10 40 downloaded from: http:/// 78m6618 data sheet ds_6618_005 30 rev. 1. 4 6 o rdering i nformation table 29 : ordering information part p art description (package) flash size pack aging orde r number package marking 78m6618 68 - pin qfn ( lead (pb) - free ) 128 kb bulk 78m6618 - im/f 78m6618 - im 78m6618 128 kb bulk, * programmed 78m6618 - im/f/p 78m6618 - im 78m6618 128 kb tape and reel 7 8m6618 -im r/f 78m6618 - im 78m6618 128 kb tape and r eel, * programmed 7 8m6618 -im r/f /p 78m6618 - im * contact maxim for more information on programmed part options. 7 contact information for more information about maxim products or to check the availability of the 78m6618 , contact technic al support at www.maxim -ic.com/support . downloaded from: http:/// ds_6618_005 78m6618 data sheet rev. 1. 4 31 8 appendix a: acronyms ansi american national standards institute ce compute engine dio digital i /o ice in - circuit emulator iec international electrotechnica l commission mpu microprocessor unit (cpu) pll phase - locked l oop r ms root mean square sfr special function register soc system on chip uart universal asynchronous receiver/transmitter downloaded from: http:/// 78m6618 data sheet ds_6618_005 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no c ircuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products. 9 revision history revision number revision date description pages changed 1.0 5/6/2009 first publication . ? 1.4 3/11 in section 1.13, added text changes and figure 3. 10 in section 2, electrical specifications, added guarantee d by design information. 19 ? 23 in section 7, added the new contact information. 30 downloaded from: http:/// |
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